Digital ASIC Design Engineer – 5G Infrastructure

Job Description:

Join our client’s Digital ASIC Design Team to shape the future of mobile network infrastructure products, powering next-generation 5G connectivity. In this role, you will specialize in backend ASIC design and static timing analysis (STA) while thriving in an Agile work environment.

While the client is based in Sweden, this role is fully Remote

Responsibilities:

• Lead synthesis, timing/area/power optimization, and ensure timing sign-off for low-power designs.
• Develop timing constraints, execute place and route, perform equivalence checking, and oversee physical implementation.
• Collaborate with cross-functional teams to foster continuous improvement and knowledge exchange.

Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Minimum of 5 years of experience in backend ASIC design.
• Proficiency in EDA tools, static timing analysis, and timing sign-off processes.
• Expertise in low-power design methodologies, UPF, and hardware description languages (VHDL/System Verilog), along with scripting languages (Python, Perl, TCL).
• Familiarity with Synopsys tools (Design Compiler, FusionCompiler, PrimeTime).
• Experience with UNIX/Linux environments and version control systems (e.g., Clear Case, Git).
• Strong communication skills in English and a quality-focused approach to work.

Preferred Qualifications:

• Knowledge of multi-core CPU architectures, mobile communication standards, and telecommunications.
• Experience with Synopsys Spyglass, Design Compiler, and Formality.

Opportunities:

• Engage in innovative backend design projects at the forefront of technology.
• Enhance your professional skills in a supportive and collaborative environment.